1. Field of the Invention
The present invention relates to an interpolation digital filter for an audio CODEC (coder and decoder), and in particular to an improved interpolation digital filter for an audio CODEC which is implemented by a bit serial method for an audio CODEC system with a clock signal of 256 FS.
2. Description of the Background Art
As shown in FIG. 1, the known audio CODEC interpolation digital filter includes a parallel/serial converter 101 for receiving a parallel data signal DIN and outputting a serial data signal C1, a first up-sampling unit 102 for receiving the serial data signal C1 and quantizing them with the two times sampling frequency and outputting a first sampling signal C2, a first digital filter 103 for filtering the first sampling signal C2 and outputting the first filtering signal C3, a second up-sampling unit 104 for outputting a second sampling signal C4 which is obtained by quantizing the first filtering signal C3 with the two times sampling frequency, a second digital filter 105 for filtering the second sampling signal C4 with four times sampling frequency and outputting a second filtering signal C5, and a filter unit 106 for receiving the second filtering signal C5 and outputting a parallel data signal DOUT. The above-described elements are connected in serial.
As shown in FIG. 2, the filter unit 106 includes a third up-sampling unit 201 for receiving the second filtering signal C5 and outputting a third sampling signal C6, a third digital filter 202 for receiving the third sampling signal C6 and outputting a third filtering signal C7, and a serial/parallel converter 203 for receiving the third filtering signal C7 and outputting the parallel data signal DOUT.
The third up-sampling unit 201 includes a multiplexer 2 for receiving the second filtering signal C5 at one input terminal outputting a third sampling signal C6, and a delay unit 4 for receiving the third sampling signal C6 and outputting an output signal C61 to the other input terminal of the multiplexer 2. The third sampling signal C6 comprises a twice delayed serial data signal type compared to the second filtering signal C5. As above described, the first and second up-sampling units 102 and 104 are similar to the third up-sampling unit 201.
The third digital filter 202 includes a first adaptor 6 for receiving the third sampling signal C6 and outputting a first adaptor output signal C71, a second adaptor 12 for receiving the third sampling signal C6 and outputting the second adaptor output signal C73, delay units 8 and 10 for delaying the third sampling signal C6 composed of stereosignals(left and right signals) by a switch SW1, which is connected with the first adaptor 6, similarly, delay units 14 and 16 for delaying the third sampling signal C6 with stereosignals(composing with left and right signals) by a switch SW2, which is connected with the second adaptor 12, a delay unit 18 for delaying a first adaptor output signal C71 from the first adaptor 6 for a predetermined time for thereby generating a delayed output signal C72, and an adder 20 for adding the delayed output signal C72 and the second adaptor output signal C73 and generating a third filtering signal C7. In addition, the first and second digital filters 103 and 105 are configured identically to the third digital filter 202, as above mentioned.
The operation of the known interpolation digital filter will now be explained with reference to FIG. 3.
FIG. 3 is a table illustrating a conversion process of a sampling data signal by the known interpolation digital filter and a process that a parallel data signal of 32 bits of the sampling frequency 8 FS is generated by quantizing and filtering the serial data signal of 32 bits several times.
As shown therein, the row denotes the sampling time t, and the column denotes an input/output signal from each block in the interpolation digital filter.
For the input data signal is a stereo signal (the left and right data signal indicating as LiRi where L=1, 2, . . . ), when processing the parallel data signal of 32 bits of 1 Fs into a parallel data signal of 32 bits of 8 FS which comprises the quantization of an 8-times sampling frequency, the frequency of the clock signal should be supplied as 512 FS. In other words, since the sampling operation should be performed 8 times between the first input data signal L1R1 and the second input data signal L2R2, the time Tp between the sampling data signals is 32.times.2.times.8, i.e., 512 FS.
The serial data signal C1 from the parallel/serial converter 101 receiving a parallel data signal DIN is a type of the data signal sequence (L1R1, L2R2, . . . ), and the first filtering signal C3 is a type of data signal sequence (L21R21, L22R22, . . . ) which is obtained when the serial data signal sequence(L1R1, L2R2, . . . ) is quantized with a two-times sampling frequency and filtered through the first upsampling unit 102 and the first digital filter 103. The second filtering signal C5 is a type of data signal sequence (L31R31, L32R32, L33R33, L34R34, L35R35, . . . ) which is developed when the data signal sequence (L21R21, L22R22, . . . ) is quantized with a two-times sampling frequency and filtered through the second up-sampling unit 104 and the second digital filter 105. As a result, the data signal sequence (L31R31, L32R32, L33R33, L34R34, L35R35, . . . ) is a 32-bit data signal sequence of the 4 FS which is 4-times the serial data signal C1. Similarly, the parallel data signal DOUT is a type of data signal sequence (L41R41, L42R42, L43R43, L44R44, L45R45, L46R46, L47R47, L48R48, . . . ) which is developed by up-sampling and filtering the data signal sequence(L31R31, L32R32, L33R33, L34R34, L35R35, . . . ) of the 4 FS.
Therefore, the 32-bits data signal of the 1 FS is processed to the 32-bits data signal of the 8 FS. However, the above-described method is implemented by using a phase locked loop(PLL) with a clock signal of the 512 FS, the known interpolation digital filter is costly high and the size of it is increased.